Research and Thesis Projects

Neural interfaces are aimed at creating links between neurons and computers, enabling advanced electrophysiology studies and opening paths to restoring lost functions in the nervous system. CMOS technology allows for low-noise recording from thousands of electrodes in parallel, either in-vitro or in-vivo. We are developing CMOS neural interfaces integrating different functionalities, including the detection of action potentials, stimulation of neurons, or impedance imaging. In this context, we can offer Master theses and semester projects tailored to the experience and interests of the student. These project may be, for example: - Design of the analog front-end for a CMOS neural interface in 180nm. This may include the design of low-noise amplifiers, filters, analog to digital converters, sigma-delta modulators, etc. Potential tasks would be: system design, circuit design and simulation, noise/power/area optimization, layout, parasitics extraction, post-layout simulations. - Design of a LVDS buffer for high-speed (>1Gbps) communication between the neural interface and the PC. Potential tasks would be: circuit design and simulation, speed/power optimization, LVDS receiver selection, PCB design. - Design of the on-chip digital signal processing and control logic. Potential tasks would be: VHDL/Verilog coding, synthesis, place and route, area/power optimization, simulation. Students interested in PCB design, programming or signal processing are also encouraged to contact me for other possible projects. The position is located in Basel and is available for master's thesis and semester projects throughout the year. Part-time remote work arrangements can be discussed.

Dr. Fernando Cardes (Fernando.cardes@bsse.ethz.ch)

Digital signature circuits are used to verify authenticity, ensure data integrity, and prevent tampering in applications ranging from secure boot to hardware-based identity verification. This project offers the opportunity to design and evaluate such a circuit with the goal of integrating it into a chip. The student will begin by exploring various interpretations of what a signature circuit can be, considering both functional and architectural perspectives. While the final implementation may include standard cryptographic components such as SHA-256 for hashing and RSA for public-key encryption, the exact structure is open to exploration. The student is expected to propose and justify a design that balances performance, area, power consumption, and security. A key part of the project will be the evaluation of security, including resistance to side-channel attacks and fault injection. The student will also consider how the circuit fits into a broader chip architecture, including synthesis, layout constraints, and key management. This is a hands-on project that combines digital design, cryptographic engineering, and hardware security. It is ideal for students with an interest in secure systems, embedded hardware, and low-level cryptographic implementation.

Dr. Fernando Cardes

This project, building on our recent publication [1], focuses on fighting deepfakes through in‑sensor cryptographic signature generation. The goal is to embed a lightweight but secure digital signature mechanism directly inside a CMOS sensor, ensuring data authenticity at the moment of capture. The student will explore different architectural approaches to implementing the signature circuit. Depending on background and interests, the work may involve VLSI‑focused tasks (such as circuit architecture selection, synthesis, and layout considerations) or more security‑centric topics, including the use of cryptographic primitives (e.g., SHA‑256, lightweight hash functions), hardware key management, and the integration of PUF‑based key derivation. The design space is intentionally open, welcoming contributions from students in VLSI design, embedded systems, and cybersecurity alike. This project offers a hands‑on blend of digital design, cryptographic engineering, and system‑level hardware security. It is well suited for students interested in secure sensor pipelines, low‑level cryptography, and silicon‑rooted defenses against content forgery. [1] Cardes, F., Bürgel, S., Yuan, X. et al. In-sensor cryptographic signature generation to link a physical process and an immutable digital entity. Nat Electron (2026). https://doi.org/10.1038/s41928-026-01593-5

Dr. Fernando Cardes

We are offering several projects centered around the in vitro culture of neurons on CMOS microelectrode arrays (MEAs). These high-density MEAs allow for detailed, non-invasive recordings of neuronal activity, enabling the study of network dynamics, development, and responses to stimuli or pharmacological agents. The projects are ideal for students with a background in biology, biotechnology, biomedical engineering, or related fields. Prior experience in sterile techniques and cell culture is highly desirable. Depending on your interests and skills, your project may involve: - Optimizing neuronal culture protocols on CMOS MEAs - Long-term monitoring of neuronal development and activity - Pharmacological modulation of network behavior - Data analysis of electrophysiological recordings - Integration with imaging or stimulation techniques You will work in a collaborative and supportive environment with access to state-of-the-art facilities and mentorship from experienced researchers. The specific research question and methods will be defined together with you, allowing for a personalized and meaningful research experience. The position is located in **Basel** and is available for master's thesis and semester projects throughout the year.

Dr. Fernando Cardes | fernando.cardes@bsse.ethz.ch

In vitro studies using high-density CMOS microelectrode arrays (MEAs) enable groundbreaking insights into the functioning of neural networks outside the living body. These advanced tools provide unparalleled spatial and temporal resolution, allowing researchers to: - Study Neural Dynamics: Precisely observe neuronal behavior, connectivity, and activity in controlled environments. - Advance Drug Discovery: Test drug efficacy and safety in vitro before progressing to in vivo studies. - Understand Neurological Disorders: Explore the mechanisms underlying conditions such as epilepsy, neurodegeneration, and psychiatric disorders. High-density CMOS MEAs play a vital role in capturing complex neural signals with high fidelity. Advanced software solutions are essential for enabling key functionalities, such as allowing experimenters to select specific areas of neural tissue for study, or visualizing neuronal signals in real time. **Key Responsibilities** - Develop, optimize, and maintain software for in vitro neural studies using CMOS MEAs. - Implement algorithms for real-time neural data acquisition, processing, and visualization. - Enhance usability and functionality of software for researchers conducting experiments. - Collaborate with neuroscientists and engineers to align software with research needs. - Create clear, user-friendly documentation for software tools and workflows. **Requirements** - Proficiency in Python; C++ and MATLAB knowledge is a plus. - Strong documentation skills for clear, user-friendly guides. - Effective communication and teamwork for interdisciplinary collaboration. **Location & Application** This internship is for a 6-month duration, with flexible options for remote or on-site work (in Basel, Switzerland) based on project requirements and candidate preferences. Applicants should submit a CV highlighting relevant experience in software development. Additionally, please include information about availability, specifying when you would be ready to start. While the position is open immediately, the actual start date will depend on administrative processes. Incomplete applications will not be considered. This project is available as Master thesis or semester project.

Dr. Fernando Cardes fernando.cardes@bsse.ethz.ch

High-density CMOS MEAs are versatile tools used in neuroscience that high-resolution recordings of neural activity. To fully leverage these capabilities, custom PCBs are required to manage high-speed data transfer, power delivery, and signal routing. This project focuses on: - Designing PCBs to interface with CMOS MEAs for neural signal acquisition. - Ensuring signal integrity and minimizing noise in high-speed circuits. - Validating and testing boards in lab environments. - Optionally, developing firmware and/or software to control the electronics and enhance the functionality of these neural interfaces. Requirements - Experience with PCB design tools (Altium preferred). - Understanding of high-speed electronics and signal integrity. - Strong documentation and communication skills. - Ability to work independently and in teams.

Dr. Fernando Cardes

Measurement of transepithelial electrical resistance (TEER) is a widely used method to assess tight junction integrity in in vitro barrier models without compromising tissue viability. While several commercial systems exist, they are primarily designed for static culture formats such as Transwell inserts and are not suited for continuous, real-time monitoring of barrier responses under dynamic conditions. As part of the **NCCR AntiResist** consortium, we have developed a novel microfluidic platform (https://doi.org/10.1002/admt.202400326) that enables the transition of transwell-grown epithelial tissues from static to perfused environments. This allows for more physiologically relevant modeling of human tissues. The device is currently used to study stem cell-derived bladder models in the context of urinary tract infections (UTIs), where pathogen invasion can lead to varying degrees of barrier disruption, modulated by therapeutic intervention. Current methods for assessing barrier function rely on: - **High-resolution confocal microscopy** - **Permeability assays using fluorescent tracers** While informative, these approaches provide only discrete, time-point-specific data. To overcome this limitation and enhance temporal resolution, we have integrated a prototype impedance-based TEER sensor into the microfluidic chip for continuous, non-invasive monitoring of barrier integrity: https://doi.org/10.1109/SENSORS60989.2024.10785013 The focus of this project is the **further development and validation** of this integrated TEER system, including: - **Electrode design optimization**: Refine electrode geometry, spacing, and materials to maximize signal sensitivity, stability, and compatibility with fluidic environments. - **System characterization under biological conditions**: Evaluate sensor performance using tissue models with both intact and compromised barrier function under varying flow rates, media conditions, and treatment regimens. - **Validation against standard assays**: Benchmark impedance-based readouts against traditional techniques (e.g., confocal imaging, permeability assays) to ensure biological relevance. - **Implementation in infection models**: Replicate infection protocols with uropathogenic *E. coli* under perfusion, and quantify real-time changes in barrier integrity during infection and recovery with therapeutics. - **Development of a robust data analysis pipeline** This is an **interdisciplinary project**, offering hands-on experience in: - Mammalian cell and tissue culture (including stem-cell-derived epithelial models) - Microfabrication and cleanroom techniques - Electrical measurements and sensor integration - Bacterial infection assays under dynamic flow - Advanced microscopy - Data analysis and visualization **Preferred background** (at least two of the following): - Solid understanding of electronics or signal processing - Programming experience (Python, MATLAB) - Experience in microfabrication or cleanroom work

- Design and fabricate TEER sensors compatible with integration into microfluidic chips - Characterize the electrical performance and sensitivity of the integrated sensors - Use the system to monitor cellular barrier formation and disruption in real-time - Develop and implement a method for analyzing multi-frequency TEER data to extract biologically meaningful parameters

akurmashev@ethz.ch odysseas.chaliotis@bsse.ethz.ch